1. Field of the Invention
The present invention generally relates to a latch-up verifying method and a latch-up verifying apparatus for verifying layout data of a semiconductor integrated circuit. More specifically, the present invention is directed to latch-up verifying method/apparatus capable of varying an over-sized region, depending upon structural conditions and also electric characteristics of semiconductor integrated circuits.
2. Description of the Related Art
Very recently, while semiconductor integrated circuits are manufactured in very fine manners, occurrence potentials of erroneous IC operations caused by a so-called xe2x80x9clatch-upxe2x80x9d phenomenon are increased. In a CMOS (complementary MOS) semiconductor integrated circuit, it is normally known that a xe2x80x9clatch-upxe2x80x9d phenomenon occurs. That is, while such CMOS semiconductor integrated circuits are manufactured in a very fine manner and in a high integration, parastic transistors are formed. Under such a circumstance, when such a phenomenon happens to occur that a base current along a forward direction may flow through any one of a PNP transistor and an NPN transistor, which constitute a CMOS semiconductor integrated circuit, both the PNP transistor and the NPN transistor are simultaneously turned ON to be therefore brought into a positive feedback condition. Thus, these ON states of the PNP/NPN transistors are not ceased unless supplying of electric power to these transistors is interrupted.
As one of effective solving items, there is a latch-up verifying method executed based upon layout data.
This sort of conventional latch-up verifying method is described in, for instance, Japanese Laid-open Patent Application No. Hei-7-130965 opened in 1995. Concretely speaking, this conventional latch-up verifying method is constituted by: at least a well region extracting step; a transistor region extracting step; a substrate contact region extracting step; an over-sizing executing step; and a latch-up verifying step. This conventional latch-up verifying method employs the distance between the substrate contact region and the transistor region as the verifying material.
Next, one conventional latch-up verifying method will now be explained.
FIG. 13 is a flow chart for describing this conventional latch-up verifying method. This conventional latch-up verifying method verifies as to whether or not a distance between a substrate contact region and a transistor region is equal to such a distance which can sufficiently avoid an occurrence of a so-called latch-up phenomenon in accordance with a preset over-sizing value. This over-sizing value is previously set based upon input layout data D1. As a result, latch-up verification data D12 is obtained. In other words, this conventional latch-up verifying method is constituted by: a step S1 for extracting a well region; a step S2 for extracting a transistor region; a step S3 for extracting a substrate contact region; a step S16 for executing a so-called xe2x80x9cover-sizing stepxe2x80x9d, namely for drawing a safe range from the substrate contact region by using a value set every process; and also a latch-up verifying step S7 for verifying as to whether or not the transistor region is not deviated from, or is sticking out from the over-sized region, i.e., the safe range.
Next, operations of the above-explained latch-up verifying method with employment of the above-described steps will now be explained in detail.
At the first step S1, the well region is extracted based on the input layout data D1. Next, the transistor region is extracted based upon the input layout data D1 at the step S2. At the subsequent step S3, the substrate contact region is extracted based on the input layout data D1. At the step S16, the safe range (namely, over-sized region) from the substrate contact region is drawn based upon the various data extracted from the step S1, the step S2, and the step S3, while employing a constant value set every process as over-sized data, and then the over-sizing step is executed. The latch-up verification defined at the step S7 is executed. That is to say, the logic calculation is carried out between the safe range where the over-sizing step is executed at the step S16, namely the substrate contact region enlarged (over-sized) by the over-sizing step, and the transistor region extracted at the step S2. As a result, the transistor region existing outside the over-sizing region of the substrate contact region set in the above-explained over-sizing step is extracted. As a result of the extracting execution of this step S7, the latch-up verification resultant data D12 is obtained.
However, this conventional latch-up verifying method owns the following problem. That is, since the over-sizing value is set to such a constant value with respect to each process, the latch-up verification cannot be executed in high precision.
The present invention has been made to solve the above-described problem of the conventional latch-up verifying method, and therefore, has an object to provide a latch-up verifying method and a latch-up verifying apparatus, capable of executing latch-up verification in high precision.
To achieve the above-explained object, when latch-up verification for layout data is carried out, a well region, a transistor region, and a substrate contact region are extracted from the layout data. Thereafter, an over-sized region is set by (respectively) separately setting over-sizing values based upon the extracted information of the above-explained regions, and by executing an over-sizing step for the substrate contact region. Then, the latch-up verification can be executed in high precision by judging as to whether the transistor region is contained in this over-sized region.
A latch-up verifying method, according to a first aspect of the present invention, is featured by that a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information, whereby latch-up verification of the layout data is executed.
In accordance with the above-described arrangement, since the over-sized values are separately set based upon the respective extracted information of the well region, the transistor region, and the substrate contact region from the layout data of the semiconductor integrated circuit formed on the semiconductor substrate, the judgement can be carried out by considering various conditions. As a result, the latch-up verification can be done in high precision. In other words, an occurring risk of such a latch-up phenomenon will largely depend upon the structural condition and the current capability (electric characteristic). The structural condition is defined from the positional relationship among the respective regions, for instance, the distance of the region from the well region; and further defined from the conductivity type of the semiconductor substrate, the carrier density, and the dimension of the contact region. As a result, since the over-sizing region is set by considering these conditions, the latch-up verification precision can be largely increased.
Also, a latch-up verifying method, according to a second aspect of the present invention, is featured by such a latch-up verifying method of the first aspect, wherein: the latch-up verifying method is comprised of: a step for forming a database used to store an over-sizing value; a first extraction step for extracting a well region from the layout data; a second extraction step for extracting a transistor region from the layout data; a third extraction step for extracting a substrate contact region from the layout data; an over-sizing determining step for determining an over-sizing value based upon the extracted information obtained from the first extraction step to the third extraction step with reference to the over-sizing value database; a step for defining an over-sized region based upon the over-sizing value; and a step for executing the latch-up verification by checking as to whether or not the transistor region is contained within the over-sized region defined at the definition step.
In accordance with the above arrangement, while the over-sizing value is saved in the database, the over-sizing value is determined based on the extracted information of the well region, the transistor region, and the substrate contact region with reference to the over-sizing value database. As a result, the latch-up verification can be carried out in very high precision similar to the first aspect.
Also, a latch-up verifying method, according to a third aspect of the present invention, is featured by such a latch-up verifying method of the second aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value based upon any one of a structural condition and a use condition as to each of the transistor regions of the semiconductor integrated circuit.
In accordance with the above arrangement, the over-sizing value is determined based upon either the structural condition or the electrical characteristic of each of the transistor regions provided in the semiconductor integrated circuit. As a result, the latch-up verification can be carried out in very high precision.
Also, a latch-up verifying method, according to a fourth aspect of the present invention, is featured by such a lath-up verifying method of the third aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value based upon a position relationship among the transistor region, the well region, and the substrate contact region.
Also, a latch-up verifying method, according to a fifth aspect of the present invention, is featured by such a latch-up verifying method of the fourth aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value based upon a distance defined between the well region and the transistor region.
Also, a latch-up verifying method, according to a sixth aspect of the present invention, is featured by such a latch-up verifying method of the fourth aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value based upon a distance defined between the well region and the substrate contact region.
In accordance with the above arrangement, the over-sizing determining step determines the over-sizing value based upon the positional relationship among the transistor region, the well region, and the substrate contact region. As a result, the latch-up verification can be carried out in very high precision. For instance, the shorter the distance between the region and the well edge is decreased, the smaller the latch-up phenomenon occurs. As a result, the occurrence condition of such a latch-up phenomenon may largely differ, depending upon the positional relationship. For example, the over-sizing value can be increased. Thus, the latch-up verification can be carried out in very high precision, while considering this positional relationship.
Also, a latch-up verifying method, according to a seventh aspect of the present invention, is featured by such a latch-up verifying method of the third aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value, while considering a dimension of the transistor region.
In accordance with the above arrangement, the over-sizing determining step determines the over-sizing value of the transistor region based upon the dimension of the transistor region. As a result, the latch-up verification can be carried out in very high precision. For instance, the larger the dimension of the transistor region is increased, the larger the over-sizing value can be increased. Thus, the latch-up verification can be carried out in very high precision, while considering this dimension of the transistor region.
Also, a latch-up verifying method, according to an eighth aspect of the present invention, is featured by such a latch-up verifying method of the third aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value, while considering a gate length and/or a gate width of the transistor region.
With employment of the above-explained arrangement, the over-sizing value is determined by considering the gate width of the transistor region and/or the gate length thereof. As a result, the latch-up verification can be carried out in very high precision. The larger the gate width becomes, the higher the current can be supplied, so that the latch-up phenomenon can hardly happen to occur. As a consequence, the larger the gate width is increased, the over-sizing value of the transistor region may be made smaller. Also, the longer the gate length is increased, the larger the channel resistance is increased, so that the latch-up phenomenon can readily happen to occur. As a result, the longer the gate length is increased, the over-sizing value of the transistor region must be made large. As previously explained, the latch-up verification can be carried out in very high precision, while considering the gate width and the gate length. Conversely, on the other hand, when the over-sizing value of the substrate contact region is adjusted, the larger the gate width is increased, the over-sizing value of the substrate contact region must be made large. It should be noted that the entire step for adjusting the over-sizing value of the transistor region can be made simpler. Alternatively, the over-sizing value of the substrate contact region may be adjusted, if required.
Also, a latch-up verifying method, according to a ninth aspect of the present invention, is featured by such a latch-up verifying method of the third aspect, wherein: the over-sizing determination step is arranged by determining the over-sizing value in correspondence with a current capability of each of the transistor regions of the semiconductor integrated circuit.
In accordance with this arrangement, the over-sizing determining step is arranged so as to determine the over-sizing value in response to the current capability of each of the transistor regions. In such a case that a larger current may be supplied, the latch-up phenomenon can hardly happen to occur. As a consequence, the over-sizing value of the transistor region may be made smaller, or the over-sizing value of the subtract contract region may be made larger. The latch-up verification can be carried out in very high precision by considering these conditions.
Also, a latch-up verifying method, according to a tenth aspect of the present invention, is featured by such a latch-up verifying method of the third aspect, wherein: the semiconductor integrated circuit is equipped with a salicide wiring structure; the substrate contact region is constituted by a via-hole-containing contact region for contacting through a via-hole within the semiconductor substrate, and a surface contact region formed on a surface of the semiconductor substrate, while does not contact through a via-hole within the semiconductor substrate; and the over-sizing determining step judges as to whether the substrate contact region is the via-hole-containing contact region, or the surface contact region, and is arranged by reducing the over-sizing value in the case that the substrate contact region is the surface contact region.
In accordance with this arrangement, in the semiconductor device equipped with the salicide wiring structure, also, the substrate contact region having no via-hole is added to the judgement subject by changing the judgement condition. In other words, the inverters of this Patent Application could find out such a fact that the substrate contact region without such a via-hole can also prevent the occurrence of the latch-up phenomenon, and thus could employ this fact. Also, a contact region where a via-hole is not formed can be formed with having a very narrow width, as compared with another contact region where a via-hole is formed. Since this contact region without such a via-hole can be formed in a very narrow region, this contact region becomes very effective. Such a xe2x80x9csurface contact regionxe2x80x9d is conducted, and the latch-up verification is carried out by considering this surface contact region. As a result, it is possible to obtain the contact structure in higher precision, whose occupied area is very small.
Also, a latch-up verifying method, according to an 11-th aspect of the present invention, is featured by such a latch-up verifying method of the first aspect, or the second aspect, the over-sizing value database is constituted by such a function that one of the structural characteristic and the electric characteristic of each of the transistor regions of said semiconductor integrated circuit is used as a parameter; and the over-sizing value is determined by the function.
Also, a latch-up verifying method, according to a 12-th aspect of the present invention, is featured by such a latch-up verifying method of the first aspect, or the second aspect, the over-sizing value database is constituted by such a table containing a parameter made of one of the structural characteristic and the electric characteristic of each of the transistor regions of the semiconductor integrated circuit; and the over-sizing value is determined by the table.
In accordance with this arrangement, the over-sizing value database is arranged by either the function or the table, in which the structural condition or the electric characteristic of the each of the transistor regions provided in the semiconductor integrated circuit is employed as the parameter. As a result, the over-sizing value can be very easily determined by this function.
Also, a latch-up verifying method, according to an 13-th aspect of the present invention, is featured by such a latch-up verifying method of the first aspect, or the second aspect, the over-sizing value along a horizontal direction is made different from the over-sizing value along a vertical direction. Also, a latch-up verifying method, according to an 14-th aspect of the present invention, is featured by such a latch-up verifying method of the firs aspect, or the second aspect, the over-sizing value at a right hand along a horizontal direction is made different from the over-sizing value at a left hand along the horizontal direction; or the over-sizing value at an upper hand along a vertical direction is made different from the over-sizing value at a lower hand along the vertical direction.
In accordance with this arrangement, the over-sizing values are set to be made different from each other along both the horizontal direction and the vertical direction, otherwise, along both the right horizontal direction and the left horizontal direction, and along both the upper vertical direction and the lower vertical direction. In other words, for instance, the safe range of the transistor region along the channel width direction is different from the safe range of the transistor region along the channel length direction. The over-sizing value of the transistor region along the channel length direction is smaller than that along the channel width direction. Since the over-sizing values are determined by considering such a direction, the latch-up verification can be carried out in very high precision.
To achieve the above-described object, a latch-up verifying apparatus, according to a 15-th aspect of the present invention, is featured in that a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information, whereby latch-up verification of the layout data is executed.
A latch-up verifying apparatus, according to a 16-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 15-th aspect, the latch-up verifying apparatus is comprised of: a database used to store an over-sizing value; first extraction means for extracting a well region from the layout data; second extraction means for extracting a transistor region from the layout data; third extraction means for extracting a substrate contact region from the layout data; over-sizing determining means for determining an over-sizing value based upon the extracted information obtained from the first extraction means to the third extraction means with reference to the over-sizing value database; definition means for defining an over-sizing region based upon the over-sizing value; and verification means for executing the latch-up verification by checking as to whether or not the transistor region is contained within the over-sizing region defined at the definition means.
A latch-up verifying apparatus, according to a 17-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 16-th aspect, the determination means is arranged by determining the over-sizing value based upon any one of a structural condition and a use condition as to each of the transistor regions of the semiconductor integrated circuit.
A latch-up verifying apparatus, according to a 18-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 17-th aspect, the determination means is arranged by determining the over-sizing value based upon a position relationship among the transistor region, the well region, and the substrate contact region.
A latch-up verifying apparatus, according to a 19-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 18-th aspect, the determination means is arranged by determining the over-sizing value based upon a distance defined between the well region and the transistor region.
A latch-up verifying apparatus, according to a 20-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 18-th aspect, the determination means is arranged by determining the over-sizing value based upon a distance defined between the well region and the substrate contact region.
A latch-up verifying apparatus, according to a 21st aspect of the present invention, is featured in such a latch-up verifying apparatus of the 17-th aspect, the determination means is arranged by determining the over-sizing value, while considering a dimension of the transistor region.
A latch-up verifying apparatus, according to a 22nd aspect of the present invention, is featured in such a latch-up verifying apparatus of 16-th aspect, the determination means is arranged by determining the over-sizing value, while considering a gate length and/or a gate width of the transistor region.
A latch-up verifying apparatus, according to a 23rd aspect of the present invention, is featured in such a latch-up verifying apparatus of the 16-th aspect, the determination means is arranged by determining the over-sizing value in correspondence with a current capability of each of the transistor regions of the semiconductor integrated circuit.
A latch-up verifying apparatus, according to a 24-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 15-th aspect, or the 16-th aspect, the over-sizing value database is constituted by such a function that one of the structural characteristic and the electric characteristic of each of the transistor regions of the semiconductor integrated circuit is used as a parameter; and the over-sizing value is determined by the function.
A latch-up verifying apparatus, according to a 25-th aspect of the present invention, is featured in such a latch-up verifying apparatus of the 15-th aspect, or the 16-th aspect, the over-sizing value database is constituted by such a table containing a parameter made of one of the structural characteristic and the electric characteristic of each of the transistor regions of the semiconductor integrated circuit; and the over-sizing value is determined by the table.
In such a latch-up verifying apparatus, the latch-up verification can be carried out in high precision.